1. Field of the Invention
The present invention generally relates to semiconductor devices, and, more particularly, to complex semiconductor devices with ferroelectric hafnium oxide, and a method for forming an according semiconductor device.
2. Description of the Related Art
Integrated circuits typically comprise a very large number of circuit elements formed on a given area of a chip, wherein a semiconductor device represents an important implementation of a circuit element. For example, current advanced ICs (integrated circuits) are formed by millions of field effect transistors, which are also referred to as MOS transistors or MOSFETS, and in general MOSFETs may be considered as dominant semiconductor devices in modern ICs. Efforts towards increased performance and low integration volume have, therefore, been mainly directed to reducing the size of basic transistor structures. A drive to continuously improve the performance of semiconductor devices is given by Moore's law of scaling, which demands that the number of semiconductor devices in an IC increases exponentially, e.g., doubling over a two or three year period. As a consequence, minimum feature sizes of transistors have decreased exponentially with about each year.
Despite a plurality of scaling reducing process technologies having been developed and practiced so as to comply with Moore's law, it is clear that scaling cannot go on forever, particularly as constraints imposed by materials become increasingly important at advanced scaling nodes. For example, the thickness of a gate dielectric layer in a gate electrode of an advanced transistor structure has become so thin (under 2 nm) that a gate leakage current caused by direct tunneling of electrons from the gate electrode into a channel region (generally located underneath the gate electrode) increases with decreasing layer thickness and, as a result, the power dissipation of any integrated circuit based on such transistors becomes unacceptable.
In using high-k dielectric materials, the gate leakage problem can be addressed by providing gate dielectrics with high-k dielectric materials, such as hafnium oxide-based materials, which allows increasing the capacitive coupling of the gate electrode to the channel without reducing the thickness of the gate dielectric. Therefore, the implementation of gate dielectrics by means of high-k dielectric materials allows not only increasing the performance of individual transistor elements, but also reducing the dimensions of semiconductor devices and consequently incorporating increased functionality into a given chip area.
Further efforts to increase the functionality built into a given chip area resulted in approaches to eliminate secondary storage systems. These approaches are based on the development of non-volatile memory devices which do not lose stored information when power supply is lost. Herein, efforts are directed to the development of ferroelectric RAMs or FeRAM devices which make use of dielectric layers with ferroelectric properties. Current FeRAMs appear to show, in comparison with conventional flash memory devices, lower power usage at higher writing performances and a greater number of write-erase cycles. Consequently, intensive investigations have been conducted to ferroelectric materials in order to provide non-volatile memory devices.
Therefore, ferroelectric materials have been considered for forming highly efficient capacitors. The effect that one makes use of herein is the possibility to adjust the polarization state of a ferroelectric material on the basis of appropriate electrical fields which are applied to the ferroelectric material. Since the polarization state of a ferroelectric material is preserved unless it is exposed to a high, with regard to the polarization state counter-oriented electrical field, or a high temperature, it is possible to “program” a capacitor formed of ferroelectric material such that an induced polarization state reflects an information unit. The reason is that an induced polarization state may be preserved, even upon removing a “programmed” capacitor from a power supply. Opposed to conventional storage capacitors of known flash memory designs, a refreshment of the state of the capacitor is not required. Another advantage of ferroelectric materials is the comparatively high dielectric constant of ferroelectric materials (k greater than 4) which may enable fabricating semiconductor devices with superior performance as compared to conventional semiconductor devices.
Although a ferroelectric field effect transistor or a ferroelectric capacitor represent in theory very promising concepts for complex semiconductor devices, it is a difficult task to identify appropriate ferroelectric materials which are compatible with existing manufacturing processes, particularly at advanced technology nodes. For example, commonly known ferroelectric materials, such as PZT or perovskites, are not compatible with standard CMOS processes. However, recent research results indicate that hafnium oxide-based dielectric materials may represent promising candidates for materials with ferroelectric behavior. To date, it is known that hafnium (Hf) rich materials exhibit a predominantly monoclinic structure with paraelectric behavior and pure HfO2 is known to be of paraelectric nature. With regard to hafnium-based materials, however, recent results indicated that the monoclinic structure is suppressed in Zr, Si, Y and Al-doped hafnium oxide materials and stabilized crystal structures of ferroelectric nature were obtained in accordingly-doped samples. Examples of ferroelectric hafnium-based materials are, for example, discussed in Mueller et al., “Incipient Ferroelectricity in Al-doped HfO2 Thin Films,” Adv. Funct. Mater., 22:2412-17 (2012), Mueller et al., “Ferroelectricity in yttrium-doped hafnium oxide,” J. Appl. Phys., 110:114113 (2011), Mueller et al., “Ferroelectricity in Simple Binary ZrO2 and HfO2,” Nanoletters, 12:4318-23 (2012), and Boeske et al., “Phase Transitions in Ferroelectric Silicon-doped Hafnium Oxide,” Appl. Phys. Lett., 99:112904 (2011).
Presently, the ferroelectric nature of some hafnium-based materials as opposed to the paraelectric nature of hafnium rich materials is considered as originating from an appropriate crystalline state being established in accordingly-doped hafnium oxide material which provides the ferroelectric nature was not observed that pure hafnium oxide does not have due to its monocline crystal structure.
Although ferroelectric material on the basis of hafnium oxide may be expected to show a better compatibility with existing CMOS processes, several drawbacks for ferroelectric non-volatile memory devices are observed in actual implementations. Particularly, the doping of a deposited ferroelectric hafnium oxide layer, for instance in the framework of an ALD process, raises a lot of issues with regard to how to include the doping of the ferroelectric hafnium oxide layer into the ALD sequence. For instance, a necessarily complex recipe structure for including dopants into ferroelectric hafnium oxide reduces the throughput of existing process flows. Particularly in ALD processes, additional doping precursors are necessary that usually suffer from low-ALD capability. It is observed that doping in ALD processes is not possible to a sufficient degree. For hafnium oxide, there is a narrow process window for establishing a ferroelectric phase by including dopants into the hafnium oxide, leading to difficult process control, for example with XPS-analysis, and bad doping uniformity. As large fluctuations of device parameters occur across wafers, it is not possible, for example, to provide sufficient memory window uniformity for ferroelectric FET devices.
In view of the above-described state in the art, it is desirable to provide a semiconductor device with incorporated ferroelectric behavior in good compatibility with standard manufacturing techniques and without deteriorated performance of fabricated semiconductor devices and lowering throughput. It is further desirable to provide a method for forming a semiconductor device with ferroelectric properties in agreement with standard CMOS processes and particularly which can be included into standard processes without inferring complex recipe structures.